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These 4 lines ever connect to holes - these gaps reduce heat conduction during soldering ground plane Change transistor footprint to inline_wide, fix DRC ground plane 56529bef3a0c7d0b31cfccd6b6ce971fb35b4e9c Updates from real TL0x4s d12ec1f19bbae8f01395e4c76a152d3d4ce7a3d4 created pull request 'new_footprints' (#5) from new_footprints into main ... Add jlc constraints DRC; replace order.

• -2.33215 2.58057 facet normal -0.499997 -0.866027.
• -6.417228e+000 9.983999e+000 vertex -2.013369e+000 5.249184e+000 9.983999e+000.
• 7.11876 4.7566 5.56266 facet normal.
• ARISING IN > ANY WAY OUT OF OR.

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