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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 ============================================================= Total unplated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-B_SilkS.gbr Normal file Unescape ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 10:22:31 2021 e6b834b08c Fix floating pin for Pause (J19/J18); the schematic is incorrect .
- Normal -8.506957e-01 1.781115e-03 5.256555e-01 vertex -1.084234e+02 9.725134e+01.
- -0.382432 0.0376698 0.923216 facet normal -0.0393352.
- Ref="R?" Part="1" AR Path="/607ED812/60B160FF" Ref="J7" Part="1" AR Path="/607ED812/60B160FF.