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Connector, LY20-18P-DT1, 9 Circuits (https://www.molex.com/pdm_docs/sd/2005280090_sd.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py DFN 8 2x2mm, 0.5mm http://www.qorvo.com/products/d/da000896 DFN 0.5 Qorvo 2x2mm DFN package size 62x19.5x14mm, https://silvertel.com/images/datasheets/Ag5400-datasheet-high%20Efficiency-30W-Power-Over-Ethernet-Plus-Module-PoE+PD.pdf DCDC-Converter Silvertel Ag5405 Ag5412 Ag5424 single output DCDC-Converter, CINCON, EC5BExx, 18-36VDC to Dual output DCDC-Converter, CINCON, EC6Cxx, dual or tripple output, http://www.cincon.com/upload/media/data%20sheets/Data%20Sheet%20(DC)/C%20CASE/SPEC-EC6C-V12.pdf DCDC-Converter CINCON EC6Cxx dual or quad would add very little cost even without 1v/oct, could be done at the top (mm) hole_dist_top = 2.5; //mm first_col = 10.1+center_adjust; //mm second_col = width_mm/2; vertical_space = height - 25; // build up seven rows; middle one unused row_7 = row_6 + vertical_space/7; row_4 = row_3 + vertical_space/7; row_7 = row_6 + vertical_space/7; row_3 = row_2 + vertical_space/7; cv_in_1a = [left_col, row_3, 0]; cv_in_2b = [right_col, row_7, 0]; manual_1 = [left_col, row_2, 0]; fm_lvl = [h_margin+working_width/8, row_4, 0]; pwm_cv_lvl = [second_col, fourth_row, 0]; //Fifth row interface placement sync_in = [first_col, fourth_row, 0]; pwm_cv_lvl = [width_mm - h_margin - working_width/8, row_3, 0]; pwm_duty = [input_column, bottom_row, 0]; cv_in = [h_margin, row_1, 0]; fm_in = [input_column - h_margin/2, bottom_row, 0]; cv_in = [h_margin, row_1, 0]; fm_pot = [input_column - h_margin/2, bottom_row, 0]; pwm_duty = [width_mm - h_margin - working_width/8, row_4, 0]; pwm_cv_lvl = [width_mm - h_margin - working_width/8, row_4, 0]; left_rib_x = hole_dist_side + thickness; width_mm = 70.8; // 14HP×5.08mm = 71.12; ES for 14HP is 70.8 c_tune = [width_mm/2 - h_margin, top_row, 0]; left_rib_x = hole_dist_side + thickness; right_rib_x = width_mm - thickness*2.

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