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BackIrd*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ ord*cos(lf0), ord*sin(lf0), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ord*cos(lf1), ord*sin(lf1), h1], [ ord*cos(lf0), ord*sin(lf0), h0], [ ord*cos(lf2), ord*sin(lf2), h0], [ ird*cos(lf1), ird*sin(lf1), h2], [ ord*cos(lf2), ord*sin(lf2), h0], [ ird*cos(lf0), ird*sin(lf0), h1], [ ird*cos(lf2), ird*sin(lf2), h1], [ 0,0,h2], Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: unplated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Correcting changed filename in .prl 54f1a61ba5 gets jiggy with PCB locator, 11 Pins per row (http://www.molex.com/pdm_docs/sd/1053101208_sd.pdf), generated with kicad-footprint-generator Molex CLIK-Mate series connector, S34B-PHDSS (http://www.jst-mfg.com/product/pdf/eng/ePHD.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py SOP, 4 Pin (https://toshiba.semicon-storage.com/info/docget.jsp?did=10047&prodName=TLP3123.
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