Labels Milestones
BackPitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=275, NSMD pad definition Appendix A BGA 324 0.8 CS324 CSG324 BGA 324 0.8 CSGA324 Artix-7, Kintex-7 and Zynq-7000 BGA, 22x22 grid, 19x19mm package, 0.8mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=268, NSMD pad definition Appendix A Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=294, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=90, NSMD pad definition (http://www.ti.com/lit/ds/symlink/tlv320aic23b.pdf, http://www.ti.com/lit/wp/ssyz015b/ssyz015b.pdf Texas Instruments, BGA Microstar Junior, 5x5mm, 80 ball 9x9 grid, NSMD pad definition Appendix A BGA 324 0.8 GateMate FPGA Maxim WLP-12, W121H2+1, 2.008x1.608mm, 12 Ball, 3x4 Layout, 0.5mm Pitch, http://www.ti.com/lit/ds/symlink/txb0104.pdf, http://www.ti.com/lit/an/snva009ag/snva009ag.pdf BGA 12 0.5 R-XBGA-N12 Texas Instruments, DSBGA, area grid, NSMD, YZP0005 pad definition, 0.8875x1.3875mm, 5 Ball, 2x3 Layout, 0.35mm Pitch, https://www.ti.com/lit/ml/mxbg383/mxbg383.pdf, https://www.ti.com/lit/ds/symlink/tps62800.pdf Texas Instruments, DSBGA, 1.43x1.41mm, 8 bump 3x3 array, NSMD pad definition (http://www.ti.com/lit/ml/mxbg270/mxbg270.pdf Texas Instruments, DSBGA, area grid, YZR pad definition Appendix A BGA 1760 1 FF1761 FFG1761 Virtex-7 BGA, 34x34 grid, 35x35mm package, 1mm pitch; https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=277, https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf#page=296, https://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf#page=91, NSMD pad definition Appendix A BGA 484 0.8 SBG485 SBV485 LFCSP, exposed pad, thermal vias, DDA0008J (http://www.ti.com/lit/ds/symlink/tps5430.pdf 8-pin HTSOP package with 1.27mm pin pitch, compatible with SOIC-8, 3.9x4.9mm² body, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline http://www.vishay.com/docs/49633/sg2098.pdf SOP, 16 Pin package with missing pin 6 8-lead though-hole mounted DIP package, row spacing 15.24 mm (600 mils), Socket 14-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), body size (see http://www.kingtek.net.cn/pic/201601201417455112.pdf SMD 4x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), LongPads THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket LongPads 22-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), LongPads 10-lead.
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