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Bin 0 -> 69774 bytes Images/precadsr-panel-art.png | Bin 0 -> 684 bytes create mode 100644 Images/PXL_20210831_001017829.jpg create mode 100644 Hardware/PCB/precadsr/fp-lib-table create mode 100755 VCO_MANUAL_v2.pdf Update luther's layout Update luther's layout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 2cb8e5eaf679e30139948d8744800b04487466fc updated C5 footprint & tracing; schematic annotation 6523065365 updates the potentiometer pads and trace routing to de-bodge the pots. 6523065365c12ceda76dbda25c5041018c73eb63 's notes on repique/caixa, two or three.

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