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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes.
- Normal 4.711472e-001 -8.098493e-001 3.495202e-001 vertex -5.964662e-001 4.277734e+000 2.475471e+001.
- (c) 2021 rhysd Permission is.
- System, 5267-05A, 5 Pins.
- 0.114168 0.990967 -0.0703566 facet normal -0.286343 0.11861 0.950757.