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22-27-2031, 3 Pins per row (http://suddendocs.samtec.com/prints/hle-1xx-02-xxx-dv-xx-xx-xx-mkt.pdf, http://suddendocs.samtec.com/prints/hle-dv-footprint.pdf), generated with kicad-footprint-generator Molex LY 20 series connector, B8B-PH-SM4-TB (http://www.jst-mfg.com/product/pdf/eng/ePH.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py PowerPAK 1212-8 Single (https://www.vishay.com/docs/71656/ppak12128.pdf, https://www.vishay.com/docs/72597/72597.pdf Vishay PowerPAK 1212-8 Single Zetex, SMD, 8 pin DIP socket | | | J3, J4, J5 | 3 | 22k | Resistor | | | | | D1, D2, D3, D4, D5, D8, D9, D10 | 8 "active_layer_preset": "All Layers", "active_layer_preset": "All Layers", "active_layer_preset": "All Copper Layers", re-re-remove the mysterious extra trace 5040873587dbb57684343269abab88d35cf7124b Update Schematics/schematic_bugs_v1.md more fixes glide fix d9235591732ea49a85db49010f2aaf63f936f2b3 re-re-remove the mysterious extra trace Binary files /dev/null and b/Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-drl_map.pdf.

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