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Registers (accidentally a pile in my collection) and the output jacks row_2 = row_1 + v_margin + 12; top_row = height - v_margin*2 - title_font_size; working_increment = working_height / 5; row_2 = row_1 + vertical_space/7; row_7 = row_6 + vertical_space/7; row_7 = row_6 + vertical_space/7; row_3 = row_2 + vertical_space/7; cv_in_1a = [left_col, row_5, 0]; audio_out_1 = [right_col, row_1, 0]; audio_out_2 = [right_col, row_2, 0]; fm_in = [h_margin+working_width/8, row_2, 0]; fm_in = [h_margin+working_width/8, row_2, 0]; cv_2b_atten = [right_col, row_1, 0]; f_tune = [width_mm/2 + h_margin, top_row, 0]; left_rib_x = thickness * 1; //right_rib_x = width_mm - h_margin; input_column = h_margin; working_height = height - v_margin - title_font_size*1.5; working_height = height - v_margin*2 - title_font_size*1.5; saw_out = [output_column, bottom_row, 0]; c_tune = [second_col, fifth_row, 0]; //left_rib_x = thickness * 2; right_rib_x = width_mm - 9.5/2 - right_rib_thickness - tolerance; // rib + half a jack col_right = width_mm - 10 ohms between U1-14 and U2-1 when off, more like 1M when off - Single Step - 12V through 10k Ohms to U-1-14, more like 1M ohms when off Single Step - 12V through 10k Ohms to U-1-14, more like 1M ohms when off Glide In - ~27K to U3-8? No, transistors maybe activate? Outs: Clock Out - 1K to U3-7 Glide section not working right, just pegging the output jacks Latest commits for file Synth_Manuals/Module Summaries.ods | Bin 0 -> 13714 bytes .../precadsr-panel-Gerbers/precadsr-panel.drl | 47 .../precadsr-panel.gbrjob | 126 .../precadsr-panel/precadsr-panel-cache.lib | 106 .../precadsr-panel-rescue.kicad_sym | 228 .../precadsr-panel/precadsr-panel.kicad_pro | 481 .../precadsr-panel/precadsr-panel.kicad_sch | 831 Hardware/Panel/precadsr-panel/sym-lib-table | 4 .../precadsr-Edge_Cuts.gbr | 30 .../precadsr_aux_Gerbers/precadsr-F_Mask.gbr | 185 .../precadsr_aux_Gerbers/precadsr-B_Paste.gbr | 4 .../PCB/precadsr_aux_Gerbers/precadsr-PTH.drl .

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