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Docs/precadsr_bom.md | 45 .../fastestenv_Jack_Hole.kicad_mod | 17 .../Bigger_Push_Switch_Hole_NPTH.kicad_mod | 13 Binary files /dev/null and b/3D Printing/Panels/BLADE BARRIER.png | Bin 9479 -> 14135 bytes caixa_sr2.png | Bin 139972 -> 140153 bytes create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-PasteTop.gtp create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-MaskTop.gts create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Jack_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Jack_Hole_NPTH.kicad_mod delete mode 100644 Hardware/Panel/precadsr-panel/sym-lib-table create mode 100644 Panels/title_test_22.stl Binary files /dev/null and b/Panels/a_color_icon_of_a_flying_fireball.webp differ Binary files /dev/null and b/Panels/FireballSpell_Large_bw.png differ Binary files /dev/null and b/caixa_sr2.png differ Latest commits for file Panels/dual_vca.scad T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: ============================================================= bacdac34d747275148c56e8293dc209c2e326fe4 0d3d72c49e606725216a5a9a4217e6c039d5a574 c9e81f0cc630cea052574ce7c50b3e82145bb626 Image of caxia score Image of caxia score caixa_sr1.png | Bin 0 -> 37432 bytes Panels/futura medium condensed bt.ttf | Bin 0 -> 38764 bytes Panels/futura light bt.ttf create mode 100644 Hardware/PCB/precadsr/precadsr.cmp create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles.kicad_mod.

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