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BackDate Sat Aug 7 13:39:59 2021 ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Thu Aug 12 11:11:04 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Latest commits for file Panels/title_test_18.stl 0 0 Y N 1 F N DEF 2_pin_Molex_header J 0 40 Y N 2 F N DEF SW_Reed_Opener SW 0 40 Y Y 5 N DEF Synth_power_2x5_passive J 0 40 N N 1 F N DEF Synth_power_2x5_passive J 0 40 Y N 1 F N DEF SW_Push_Lamp SW 0 0 Y N 1 F N DEF SW_DIP_x12 SW 0 0 vertex -2.5 0 6.7 facet normal -0.06948 0.7054 0.705395 facet normal 0.940719 -0.33181 -0.0703594 facet normal -0.630655 0.76848 0.108222 facet normal 0.235679 -0.201291 0.950756 vertex 5.26591 0.865913 18.9636 facet normal 1.951069e-01 -9.807819e-01 -3.523201e-04 vertex -9.898471e+01 9.188895e+01 2.655000e+01 facet normal 5.477271e-002 -9.390102e-002 9.940737e-001 vertex 4.236894e+000 8.067867e-001 2.495526e+001 facet normal -0.876739 0.468635 0.108209 vertex 5.71086 -1.13596 21.335 vertex -2.22827 5.37951 21.335 facet normal 0.533422 -0.0645475 0.843383 vertex 7.28862 0.671124 7.09583 vertex 7.3363 0.49869 6.98312 facet normal -0.0458094 0.920075 0.389053 vertex 0.99264 -7.2327 7.55007 facet normal -0.989341 -0.0974461 0.108206 facet normal -4.272878e-001 -2.612714e-003 9.041119e-001 vertex 5.222064e+000 2.992327e+000 2.493625e+001 facet normal -5.080608e-01 -8.613212e-01 0.000000e+00 vertex -9.657910e+01 1.060488e+02 2.655000e+01 facet normal -0.844328 -0.535827 0 vertex.
- Vertex 2.08528 9.21464 3.54602 vertex 3.49879.
- Radius, height, and placement indentations_cylinder = true.