Labels Milestones
Back7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 Not plated through holes: unplated through holes: ============================================================= 77735c00cc3285131373f5cfc61b82eab5963d12 Update README.md 32ece2d681b26731bad50902587b988d6a79e43e updated README.md updated C14 footprint, traces, groundplane master PSU/Synth Mages Power Word Stun Panel.kicad_pcb create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Bourns_3296W_Vertical.kicad_mod create mode 100644 Schematics/SynthMages.pretty/SOCKET_2_PIN_Header.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_RD901F-40-00D_Single_Vertical_CircularHoles_centered.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/PPTC_RXEF025.kicad_mod create mode 100644 3D Printing/Pot_Knobs/pot_knob_two_parts_cap.stl Normal file View File main precadsr/Docs/precadsr_bom.md 59 lines Latest commits for file Schematics/bad_trace_v1.jpeg add pic Schematics/bad_trace_v1.jpeg | Bin 0 -> 12821 bytes 3D Printing/Rails/36hp_innie.stl | Bin 0 -> 16561 bytes create mode 100644 Docs/precadsr_layout_back.pdf (grid_origin 97.28 88.9
- Pin pitch=45mm, , length*diameter=42*29.0mm^2, Electrolytic Capacitor.
- = 13.0A, Itrip=24.0A, http://www.bourns.com/docs/product-datasheets/mfrht.pdf.