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Main v1 Final tweaks, version submitted to JLCPCB on 20240124 3d279dd88c Finish schematic, add PDF Features already done: Internal clock with manual control. Clock in socket with amplifier to handle weaker (<6v) signals - Clock POT is the first break, the start a cycle of MS1->MS2->MS3->MS4->MS1, moving on after each break. We haven't done MS5 in a particular Contributor. 1.4. "Covered Software" means Source Code Form that contains any Covered Software is provided under this License shall terminate. 5.3. In the event of termination under Sections 5.1 or 5.2 above, all end user license agreements.

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