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Back# LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes unplated through holes: merged pull request 'More schematics' (#3) from schematic into main ... Add notes about wiring SW15 cross-board 9360e76802 Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Add some perfboard sections, power headers, teardrops Compare 27 commits » 2bd01a1ff2 Add schematic, start on PCB with on-board components Add correct footprints to fireball Latest commits for file Docs/build.md footprint "Perfboard_3x12" (version 20221018) (generator pcbnew footprint "PinSocket_1x03_P2.54mm_Vertical" (version 20211014) (generator pcbnew footprint "SLIDE_POT_0547" (version 20221018) (generator pcbnew From aac0a4a5b4f604add3c1ccb9d39a8956f2d60f00 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Add ground fills, fix some clearance issues, add PCB slot, more options for this service if.
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