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Realities L1 2 keahS oidaR footprint "6.3mm_NPTH_MAXJLCPCB" (version 20221018) (generator pcbnew Latest commits for file Examples/EG_MANUAL.pdf schematic start, and some example modules Latest commits for file Schematics/SynthMages.pretty/POT_2_PIN_Header.kicad_mod From 7d48e110137d43d1f6f9100282eff6558c28f26b Mon Sep 17 00:00:00 2001 Subject: [PATCH] Notes from MK's PCB livestream Notes from MK's PCB livestream Footprints: - avoid non-circular holes in footprints whenever possible; some fabs charge more for ovals vias connect through the board, connecting a trace on one side to center of package, Thorlabs photodiodes, https://www.thorlabs.de/drawings/374b6862eb3b5a04-9360B5F6-5056-2306-D912111C06C3F830/FDGA05-SpecSheet.pdf TO-92 leads in-line, narrow, oval pads, drill 0.75mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot370-1_po.pdf SSOP56: plastic shrink small outline package; 16 leads; body width 7.5 mm; (see NXP sot054_po.pdf TO-92 leads molded, narrow, drill 0.75mm (see NXP sot054_po.pdf TO-92 leads molded, narrow, drill 0.75mm (see NXP SSOP-TSSOP-VSO-REFLOW.pdf and sot505-1_po.pdf TSSOP, 8 Pin (http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-8127-AVR-8-bit-Microcontroller-ATtiny4-ATtiny5-ATtiny9-ATtiny10_Datasheet.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py LGA, 14 Pin (https://www.st.com/resource/en/datasheet/l6491.pdf), generated with kicad-footprint-generator ipc_noLead_generator.py UQFN, 20 Pin (www.ti.com/lit/ds/symlink/tps7a7200.pdf#page=36), generated with kicad-footprint-generator JST ZE series connector, SM05B-ZESS-TB (http://www.jst-mfg.com/product/pdf/eng/eZE.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py ON Semi DFN5 5x6mm 1.27P SO-8FL CASE 488A ON Semiconductor 506CE.PDF DD Package; 8-Lead Plastic VSON, 3x3mm Body, 0.5mm Pitch, https://www.adestotech.com/wp-content/uploads/AT25SL321_112.pdf#page=75 WLCSP 12 1.56x1.56 https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMM150-DS001-01.pdf WLCSP-12, 6x4 raster staggered array, 1.403x1.555mm package, pitch 0.4mm; see section 7.8 of http://www.st.com/resource/en/datasheet/DM00387108.pdf Texas Instruments, DSBGA, 3.415x3.535x0.625mm, 64 ball 8x8 area grid, YBG pad definition, 0.95x1.488mm, 6 Ball, 2x3 Layout, 0.5mm Pitch, https://www.st.com/resource/en/datasheet/stulpi01a.pdf TFBGA-64, 8x8 raster, 3.623x3.651mm package, pitch 0.4mm; see section 48.2.4 of http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001479B.pdf WLCSP-81, 9x9, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 472, 4.36x4.07mm, 81 Ball, 9x9 Layout, 0.4mm Pitch, https://pdfserv.maximintegrated.com/package_dwgs/21-100489.PDF WLCSP-25, 5x5 raster, 2.097x2.493mm package, pitch 0.4mm pad, 15x15mm, 289 Ball, 17x17 Layout, 0.8mm Pitch, https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr3/4gb_ddr3l.pdf#page=24 FBGA-78, 10.5x8.0mm, 78 Ball, 9x13 Layout, 0.8mm Pitch, https://www.st.com/resource/en/datasheet/stm32mp151a.pdf ST UFBGA-73, 5.0x5.0mm, 73 Ball, 9x9 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g071eb.pdf ST WLCSP-36, ST die ID 467, 3.09x3.15mm, 52 Ball, X-staggered 13x8 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb55vc.pdf ST WLCSP-100, off-center ball grid, ST die ID 472, 4.36x4.07mm, 81 Ball, 9x9 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32g031y8.pdf ST WLCSP-20, ST die ID 469, 4.02x4.27mm.

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