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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH 04/13] Add notes about wiring SW15 cross-board Add design rules for jlcpcb.
- Normal 0.312773 -0.467933 -0.826566 vertex -1.60745.
- -1.06598 -6.91995 10.3435 vertex.
- Type, Outer Tail, Without Ejector (https://global.kyocera.com/prdct/electro/product/pdf/5638.pdf SD Card.
- 86.4x8.3mm^2, drill diamater 1.15mm, pad diameter.