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Export' (#4) from schematic into main afea9d5a2cf23e2a33a2927086270d4d602f5a2b Final revision; added custom DRC as project file new_footprints Added hard sync to schematic, laid out PCB with exploratory 8hp layout 2d3c489f2acf0f8bdc9cf0fe8c2346d4d07472be More SR1 notation More SR1 notation 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits.

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