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Back0 3.82299 vertex 8.82707 -1.75581 4.51215 facet normal 0.392055 0.2628 0.881606 vertex 0.194578 -6.96824 6.94018 vertex 4.76054 -5.16004 6.94563 facet normal -0.0974419 -0.989341 0.108207 facet normal 0.849615 0.233255 0.473018 facet normal 3.121532e-001 -9.500318e-001 0.000000e+000 vertex -1.397929e+000 -6.975894e+000 9.983999e+000 vertex -1.660638e+000 -5.441382e+000 1.747200e+001 facet normal -0.681163 -0.725369 0.0992779 vertex -7.28969 -6.84547 0 facet normal -1.011997e-14 5.429241e-15 -1.000000e+00 d8eca8dc7e Go to file b11a8d3187 Change transistor footprint to inline_wide, fix DRC ground plane 5e32fb4fc0953f2a10f8dc9cf7a0a3653bcbf4f2 @circuitlocution.com created pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 Generated from schematic into main afea9d5a2c Final revision; added custom DRC as project file polygon (pts Final revision; added custom DRC as project file (pts Final revision; added custom DRC as project file 8976a63dc06fa25beedf8d2553931872c491047e adds README.md.
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