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Traces "solder_mask_clearance": 0.0, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta master Binary files a/3D Printing/Panels/FIREBALL VCO.png and /dev/null differ # 2-layer, 1oz copper condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == A.Type" (condition "A.Type == 'track' && B.Type == A.Type && A.Net == B.Net" condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track'" (condition "A.Type == 'track' && B.Type == 'graphic')")) # edge clearance condition "A.Type == 'via'" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'track' && B.Type == A.Type")) # 4-layer condition "A.Type == 'via'" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" (condition "A.Type == 'track' && B.Layer == 'Edge.Cuts'" condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'" condition "A.Net != B.Net" condition "A.Type == 'track' && B.Type == 'track'" (condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" (condition "A.isPlated() && B.Type == 'graphic')" (condition "A.Type == 'via' && B.Type == 'track'" (condition "A.Type == 'via' && B.Type == 'graphic')" (condition "A.Type == 'via'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == A.Type && A.Net == B.Net" condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'pad' && !A.isPlated()" condition "A.isPlated() && B.Type == 'track'" (condition "A.Type == 'pad' && !A.isPlated()" (condition "A.Type == 'via'" condition "A.Type == 'pad' && (B.Type == 'text' || B.Type == 'track'" (condition "A.Type == 'via' && B.Type == 'track'" condition "A.Type == 'via' && B.Type .

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