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BackSimulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 Latest commits for branch hard_sync Merge pull request 'new_footprints' (#5) from new_footprints into main ... Finish schematic, add PDF Features already done: Internal clock with manual control. Sequencer cascading to trigger a second sequencer's run, which then re-triggers the first. More feature ideas: Trigger out - could be other values, ceramic may work, test debouncing. Maybe enlarge footprint if needed. Subject: [PATCH 08/13] More notes Binary files /dev/null and b/Hardware/Panel/precadsr_panel.png differ Cell (black box KASSU / AO Grid is metric (mm),
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