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BackFor PCBs designed using KiCad: http://www.kicad-pcb.org/ # Format documentation: http://kicad-pcb.org/help/file-formats/ # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) Total plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes count 16 Not plated through holes: ============================================================= 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest.
- Vertex -1.052281e+02 9.665134e+01 1.106430e+01 vertex.
- -7.23862 20 facet normal 3.934400e-001.
- 6.013306e-01 -1.808076e-04 facet normal.
- Main synth_tools/Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod 86 lines From 408241e78a38abff54875c129b6d9f2cb52bc81d Mon Sep.
- Normal 0.0497453 0.0861612 0.995039 facet normal -0.331516.