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Back# Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Subject: [PATCH] A couple more GND-stitch vias Undo converting GND to GND_JMP and fix everything that broke Finished PCB, passes all passable DRCs .../Unseen Servant/Unseen Servant.kicad_pro | 6 Panels/FIREBALL VCO.png Normal file View File 3D Printing/Panels/Radio_shaek_standoff_thick.stl create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Rotary_Switch.kicad_mod delete mode 100644 Schematics/SynthMages.pretty/SOCKET_3_PIN_HEADER_NORMAL.kicad_mod From 5663c8bc865b744661cf82b1abfca64d73c0f2fa Mon Sep 17 00:00:00 2001 Subject: [PATCH] Checkpoint before trying to add picture 9f9f6acf76 Add notes about wiring SW15 cross-board Add design rules for jlcpcb Add design rules for jlcpcb 9360e76802 Add design rules for jlcpcb 4ee6887723 Add some perfboard sections, power headers, teardrops .../Unseen Servant/Unseen Servant.kicad_sch Normal file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin font.
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