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96 Ball, 9x16 Layout, 0.8mm Pitch, https://www.infineon.com/cms/en/product/packages/PG-LFBGA/PG-LFBGA-292-11/ LFBGA-100, 10x10 raster, 10x10mm package, pitch 0.5mm; see section 7.6 of http://www.st.com/resource/en/datasheet/stm32f207vg.pdf WLCSP-66, 8x9 raster, 3.767x4.229mm package, pitch 0.8mm; see section 7.4 of http://www.st.com/resource/en/datasheet/stm32f091vb.pdf WLCSP-64, 8x8 raster, 3.141x3.127mm package, pitch 0.4mm; see section 7.4 of http://www.st.com/resource/en/datasheet/DM00366448.pdf WLCSP-168, 12x14 raster, 4.891x5.692mm package, pitch 0.4mm; see section 6.8 of http://www.st.com/resource/en/datasheet/stm32f746zg.pdf WLCSP-144, 12x12 raster, 10x10mm package, pitch 0.35mm; https://datasheets.maximintegrated.com/en/ds/MAX40200.pdf WLP-9, 1.448x1.468mm, 9 Ball, 3x3 Layout, 0.4mm Pitch, https://assets.nexperia.com/documents/data-sheet/PCMFXUSB3S_SER.pdf ST WLCSP-18, ST Die ID 466, 1.86x2.14mm, 18 Ball, X-staggered 18x10 Layout, 0.4mm Pitch, https://assets.nexperia.com/documents/data-sheet/PCMFXUSB3S_SER.pdf ST WLCSP-18, ST Die ID 466, 1.86x2.14mm, 18 Ball, X-staggered 13x8 Layout, 0.4mm Pitch, https://www.st.com/resource/en/datasheet/stm32wb55vc.pdf ST WLCSP-100, off-center ball grid, ST die ID 450, 4.96x4.64mm, 156 Ball, 13x12 Layout, 0.35mm Pitch, https://www.st.com/resource/en/datasheet/stm32h747xi.pdf DFN, 6 Pin (https://www.renesas.com/us/en/document/psc/package-drawing-hodfn-6pin-l615x16?language=en&r=568376 Miniature Crystal Clock Oscillator TXCO Fordahl DFA S11-OV/UOV, http://www.iqdfrequencyproducts.com/products/details/iqxo-70-11-30.pdf, hand-soldering, 19.9x12.9mm^2 package Miniature Crystal Clock Oscillator TG2520 series, https://support.epson.biz/td/api/doc_check.php?dl=app_TG2520SMN&lang=en Latest commits for branch panel_tweaking Add scad for v3.2 3afa35e4b1 PCB initial layout, no traces "min_copper_edge_clearance": 0.0, PCB initial layout, no traces "silk_line_width": 0.15, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "other_line_width": 0.15, PCB initial layout, no traces PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces "silk_line_width": 0.15, "silk_text_italic": false, "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, "silk_text_thickness": 0.15, "silk_text_upright": false, "zones": { "min_clearance": 0.5 } }, updates to rev 2 beta by adding +5V, and both trigger/gate and CV lines? **UI:** - 3 x switching (normalling) stereo jack (T/TN/R/RN/S/SN), https://www.neutrik.com/en/product/nj6fd-v 6.35mm (1/4 in) Vertical Jack, 2 Poles (Mono / TS), Switched T Pole (Normalling) | | | | | L1 | 1 | Conn_01x02 | SIP socket, 2.54 mm, 1x7 Pin socket, 2.54 mm, 1x2 (see [build notes](build.md)) | | J2 | 1 | B10k | **Potentiometer, 16 mm pots had long enough terminals, barely, to poke through the use or inability to use GitHub repository https://github.com/holmesrichards/precadsr Submodules git clone --recurse-submodules.

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