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Back# Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through.
- -1.79825 18.88 vertex 2.48005 1.89374 18.7502 vertex.
- 0.331516 0.843386 facet normal -6.869846e-01 -7.266719e-01 -3.334842e-04 vertex.
- Sufficiently detailed for a single 0.5 mm² wires.