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Back(type padvia min_thickness 0.0254) (filled_areas_thickness no min_thickness 0.25) (filled_areas_thickness no Latest commits for file Panels/10_step_seq.png Latest commits for file Schematics/SynthMages.pretty/Perfboard_1x12.kicad_mod # Temporary files *.000 *.bak *.bck *.kicad_pcb-bak *.kicad_sch-bak *-backups *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: merged pull request 'More schematics' (#3) from schematic by Eeschema 5.1.10-88a1d61d58~88~ubuntu20.04.1 | Refs | Qty | Component .
- -3.789330e-001 5.612119e+000 1.747200e+001 facet normal 0.988483 0.0979878 0.115323.
- 5.62839 4.67928 7.09583 vertex -7.3363 0.49869.