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Back*/fp-info-cache *.kicad_prl *.sch-bak *~ _autosave-* *.tmp *-save.pro *-save.kicad_pcb fp-info-cache *.lck # KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole Total plated holes count 16 ============================================================= Total unplated holes count 16 Not plated through holes are merged with plated holes unplated through holes: ============================================================= 2cddc4d62d38c9e1b69839f92a19e7915eecbceb 531ebcae92ad8ad00635060e3583259ee13cc12b Add html test version b22080a808 More experimentation with panel title fonts } STLs, 10hp version, others schematics b404e3f9c5 Update luther's layout