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Back# KiCad backups folders *-backups # Compressed files *.zip # Mac stuff *.DS_Store # Emacs temps *~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= f51b7b97734e404127fa5d5d263acbfd66f116e4 Add schematic, start on PCB sandwich, making some final-ish decisions about connecting to front panel 24ca7abc85681936397a2802c8155420fcaf679c updated C14 footprint, traces, groundplane 82024e96c9b263a83b6caf715e8607e9cf1b7d77 updated README.md 3e868f13c4dc33c20ca33a0cc8f51c9d63e1c081 updated C14 footprint, traces, groundplane updated C14 footprint, traces, groundplane 2cbdb94ba9 updated C5 footprint & tracing; schematic annotation updated C5 footprint & tracing; schematic annotation updates the potentiometer pads and trace routing to de-bodge the pots. Updates the potentiometer pads and trace routing to de-bodge the pots. From dd8fda85b17279e6d8dbcb525c226736e6399cf9 Mon Sep 17 00:00:00.
- DO-41 D3, D4, D5, D8, D9.
- Fireball/Fireball.kicad_pcb create mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_Cu.gbr.