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Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole Total plated holes count 16 Not plated through holes are merged with plated holes count 0 Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CmtUser.gbr Normal file Unescape Hardware/PCB/precadsr_aux_Gerbers/precadsr-F_SilkS.gbr Normal file Unescape Hardware/PCB/precadsr/precadsr.sch Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIP-8_W7.62mm_Socket_LongPads.kicad_mod Normal file View File Images/PXL_20210831_001017829.jpg Normal file Unescape Hardware/Panel/precadsr_panel_al/precadsr_panel_al.pro.

• (end 152.35 113.4 (end 177.85 73 (end 175.26.
• -2.37646 18.4724 facet normal.
• -0.500093 0.865972 -7.30812e-05 facet normal -2.890006e-001.
• 5.51093 -5.51093 5.97318 vertex 1.56356 -7.34655 6.0001.
• -5.26759 -5.16186 6.86461 vertex -5.23616 5.23616 6.86814.

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