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Back"Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 ============================================================= Total unplated holes count 16 Latest commits for file Schematics/SynthMages.pretty/Perfboard_4x12.kicad_mod // Diameter of the arrow. Scale([engraved_indicator_scale * 0.3, engraved_indicator_scale * 0.3]) union() { Panels/luther_triangle_10hp_pcb_holder.stl Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/DIP-16_W7.62mm_Socket_LongPads.kicad_mod Normal file Unescape width = 36.
- Normal -2.537102e-001 4.349550e-001 8.639706e-001 facet normal 9.964592e-01 8.406732e-02.
- Normal -0.881927 0.471385 0 facet normal 0.0110255.
- DirectFET S2 MOSFET Infineon DirectFET M2 MOSFET Infineon.
- -7.75279 -1.99403 19.9467 vertex -7.73568 -2.38614.