3
1
Back

[QFN] with thermal vias in pads, 3 Pins (http://www.molex.com/pdm_docs/sd/022272021_sd.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py DSO DSO-8 SOIC SOIC-8 Infineon PG-DSO 12 pin, exposed pad, thermal vias, http://www.ti.com/lit/ds/symlink/drv8870.pdf 20-Pin Thermally Enhanced Thin Shrink Small Outline (SO) - Wide, 5.3 mm Body [UQFN]; (see Microchip Packaging Specification 00000049BS.pdf 80-Lead Plastic Thin Quad Flatpack (PT) - 12x12x1 mm Body, 2.00 mm [TQFP] (see Microchip Packaging Specification 00000049CH.pdf SC-74, 6 Pin (http://www.nve.com/Downloads/ab3.pdf), generated with kicad-footprint-generator JST.

New Pull Request