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B/Panels/FireballSpellSmall.png differ Binary files /dev/null and b/Panels/futura medium bt.ttf | Bin 0 -> 38764 bytes Panels/futura medium condensed bt.ttf | Bin 0 -> 113418 bytes create mode 100644 Envelope/Envelope.kicad_pcb create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/Kosmo_Panel_Mounting_Hole_NPTH.kicad_mod create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/analogoutput.kicad_mod create mode 100755 Panels/FireballSpell.dxf create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/SPDT-toggle-switch-1M-series.kicad_mod delete mode 100644 Hardware/Panel/precadsr-panel/precadsr-panel.pretty/Bigger_Push_Switch_Hole.kicad_mod create mode 100644 Hardware/PCB/precadsr/potsetc.sch create mode 100644 Hardware/PCB/precadsr/Kosmo_panel.pretty/fastestenv_Panel_Mounting_Hole.kicad_mod create mode 100644 Hardware/Panel/precadsr-panel/fp-lib-table create mode 100644 Hardware/PCB/precadsr/ao_symbols.lib delete mode 100644 Hardware/PCB/precadsr/potsetc.sch create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Jack_6.35mm_PJ_629HAN.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Potentiometer_Alpha_16mm_Long_Pin_Single_Vertical.kicad_mod delete mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/Perf_Board_Hole.kicad_mod delete mode 100644 Hardware/PCB/precadsr_Gerbers/precadsr-B_Paste.gbr create mode 100644 Hardware/PCB/precadsr/ao_tht.pretty/DIP-6_W7.62mm_Socket_LongPads.kicad_mod create mode 100644 Hardware/PCB/precadsr_aux_Gerbers/precadsr-job.gbrjob create mode 100644 3D Printing/Panels/AD&D 1e spell names in Filmoscope Quentin/Panels/FIREBALL VCO.png' Delete '3D Printing/Panels/image.png' 935360b933 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png Normal file Unescape Hardware/PCB/precadsr/ao_tht.pretty/SolderWirePad_1x01_Drill0.8mm.kicad_mod Normal file Unescape f33ea6a168 Go to file f45c980890 Align panel to integer pseudo-origin, remove testing text, decrease title label font size to 9mm and align it precisely for repeatability synth_mages:v1.0 Cumulative fixes from v1.1 74231bd333b049ab7b99365de62d937af76b0e42 Finish PCBs Checkpoint after tweaking footprints some more, starting over at 14hp PCB initial layout, no traces "min_copper_edge_clearance": 0.0.

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