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Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains T1 3.200mm 0.1260" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes) T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= d952ec97f3d5e1172c33dcefe438ee5d18f8d87d Start of LM13700 version to see why 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0

== A.Type")) # 4-layer condition "A.Type == 'via.
Normal 2.947893e-004 -5.105900e-004 -9.999998e-001 facet normal.

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