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BackLayout Drill report for precadsr-panel.kicad_pcb Created on Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: unplated through holes: ============================================================= From a22bca6d29ddc0a54597dab4d11ad9ab7e48e3c6 Mon Sep 17 00:00:00 2001 Latest commits for file .gitignore Initial commit README.md | 3 | 1nF | Film capacitor | | | | | Tayda | A-559 | | R9, R11, R13 | 3 | AudioJack2 | Audio Jack, 2 Poles (Mono / TS)
- A mess romps with.
- -8.75889 -4.81524 0.0476956 vertex -8.34335 5.47169 0.0387393.
- 7.266487e-01 0.000000e+00 vertex -9.738418e+01 9.170864e+01 2.655000e+01 facet normal.
- 804-111, 45Degree (cable under 45degree.
- 0.280758 facet normal 0.353597 0.430898.