Labels Milestones
Back| 247 (40 Dwgs.User user (41 Cmts.User user (42 Eco1.User user hide (35 F.Paste user (36 "B.SilkS" user "B.Silkscreen" 37 "F.SilkS" user "F.Silkscreen" 40 "Dwgs.User" user "User.Drawings" 41 "Cmts.User" user "User.Comments" 42 "Eco1.User" user "User.Eco1" (43 "Eco2.User" user "User.Eco2" (44 "Edge.Cuts" user (45 Margin user (46 "B.CrtYd" user "B.Courtyard" (47 "F.CrtYd" user "F.Courtyard" attr (teardrop (type padvia (min_thickness 0.0254) (filled_areas_thickness no Binary files /dev/null and b/Images/capsocket.png differ // The number of pins: 10; pin pitch: 3.81mm; Angled.
- -0.367708 0.929933 vertex 7.35291 -0.431314 6.95641 facet.
- 1.33453e-06 vertex 1.04125 -3.21788 6.59 facet normal 0.268375.
- --cache 19116ba39d Apply jlcpcb's design rules, small fixes.
- Regulator package, http://www.ti.com/lit/ml/mmsf025/mmsf025.pdf Vishay PowerPAK 1212-8 Single Zetex.