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BackLayer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) T3 7.000mm 0.2756" (6 holes) T4 10.000mm 0.3937" (4 holes T5 15.200mm 0.5984" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes unplated through holes: ============================================================= T1 3.200mm 0.1260" (4 holes) (with 4 slots T2 5.000mm 0.1969" (1 hole) Total plated holes count 0 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 4233424 bytes create mode 100644 Hardware/Panel/precadsr_panel_al_Gerbers/precadsr_panel_al-F_SilkS.gbr From 8de432ba4663cc4e208cff778a114b9ae41e7906 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Fix for component clearance, panel thickness from printer realities Compare 4 commits » c971d0bd8b Merge pull request synth_mages/MK_VCO#5 613d1b6f7e Merge pull request 'More schematics' (#3) from schematic into main Reviewed-on: https://gitea.circuitlocution.com/synth_mages/MK_VCO/pulls/5 From d8eca8dc7ee0c083143ca1478ae7c1277063e5c9 Mon Sep 17 00:00:00 2001 Subject: [PATCH] Build images Images/PXL_20210831_000922493.jpg | Bin 0 -> 43300.
- Vertex -0.301613 -9.71631 3.26879.
- Nichicon, 6.3x3.0mm SMD capacitor, aluminum electrolytic nonpolar.
- On updating the fireball for.
- Angle USB type A, Horizontal.
- -1.052136e+02 9.665134e+01 9.114063e+00 facet normal -0.0953757.