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BackFinish PCBs d74befe391233bd8b162f7f5705c277e04d9b135 Checkpoint after tweaking footprints some more, starting over at 14hp PCB initial layout, no traces "silk_text_size_h": 1.0, "silk_text_size_v": 1.0, PCB initial layout, no traces }, More tweaks after pro review Apply jlcpcb's design rules, small fixes for those main synth_tools/PSU/PSU.md 5 lines 1e09530d97 Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png' Delete '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png Normal file View File Images/PXL_20210831_001017829.jpg Normal file Unescape Hardware/Panel/precadsr-panel-Gerbers/precadsr-panel-CuTop.gtl Normal file Unescape "Name": "Top Solder Mask" "Name": "Bottom Solder Paste" "Name": "Bottom Solder Mask" "Notes": "Type: dielectric layer 1 (from F.Cu to B.Cu)" "Name": "Bottom Silk.
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