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Back*~ \#* # LTSpice Simulations/*.log Simulations/*.raw Simulations/*.txt Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes unplated through holes: .
- System, 43045-0800 (alternative finishes: 43045-182x), 9.
- Normal -0.338932 0.181159 0.923205 vertex 5.07946.
- 0.992165 0.101034 0.0734901 vertex -5.19155 -4.11812.
- Coilcraft, XAL7030-332, 8.0x8.0x3.1mm, https://www.coilcraft.com/getmedia/0d05a05e-d55d-4a0c-911d-46bd73686633/xal7030.pdf Inductor, Coilcraft.