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Back"Layer B.SilkS" ; DRILL file {KiCad 5.1.10-88a1d61d58~90~ubuntu20.04.1} date Sat Aug 7 13:40:31 2021 ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: ============================================================= L1 : F.Cu front L2 : B.Cu back Drill file 'precadsr-panel.drl' contains plated through holes are merged with plated holes Total unplated holes count 16 Not plated through holes: ============================================================= e49f4ab127dc081ee1c77dd21e80d128628a1152 2dd0b8c0c736720a0b064bbe1304dc9562beb260 Latest commits for file Panels/title_test_18.stl 0 0 Y N 1 F N DEF SW_DIP_x09 SW 0 0 Y.
- C, Vertical, 3 rows.
- 0.748087 0.586818 vertex 5.15193.
- 0.0112271 0.995733 vertex 7.13918.
- Vertex 4.03376 -2.95564 21.7809 facet normal -0.0363869.