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Back[PATCH 13/13] re-re-remove the mysterious extra trace Add notes about wiring SW15 cross-board Add design rules for jlcpcb Add design rules for jlcpcb Add some perfboard sections, power headers, teardrops Compare 27 commits » 2bd01a1ff2 Add schematic, start on PCB Added input resistor for sync; placed everything on PCB with exploratory 8hp layout Bring in diylc and openscad design From 62cb30efbfdab918bafabca8d6c9cca52ce95eca Mon Sep 17 00:00:00 2001 Subject: [PATCH 1/2] Fix rail clearance issues, make all power traces large Fireball/Fireball.kicad_pro | 93 Fireball/Fireball.kicad_sch | 48 dd8c61c34f A couple more.
- "warning", "hier_label_mismatch": "error", "label_dangling.
- -7.828539e-001 4.226336e-001 facet normal.