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BackSocket_Arduino_Nano:1pin_Nano; EndCmp BeginCmp TimeStamp = /551D9380; Reference = P2; ValeurCmp = CONN_1; IdModule = Socket_Arduino_Nano:Socket_Strip_Arduino_1x15; EndCmp BeginCmp TimeStamp = /551D9432; Reference = P6; ValeurCmp = CONN_1; IdModule = Socket_Arduino_Nano:1pin_Nano; EndCmp Hardware/PCB/precadsr/precadsr.kicad_pcb Normal file Unescape Hardware/Panel/precadsr-panel/fp-lib-table Normal file View File Datasheets/2N3903-Motorola.pdf Executable file View File Images/precadsr-panel.png Normal file Unescape 3D Printing/Pot_Knobs/knob3433271.scad Executable file View File Panels/FireballSpell_Large_bw.png.svg Normal file Unescape Panels/10_step_seq_40hp_v1.scad Normal file Unescape 3D Printing/Cases/Eurorack Modular Case/EuroRack_Case_End_Male.png Executable file View File 3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/UNSEEN SERVANT.png' Upload files to '3D Printing/AD&D 1e spell names in Filmoscope Quentin/Panels/BLADE BARRIER.png a924f97182 Minor layout tweaks Schematics/Fireball_VCO.pdf | Bin 0 -> 144834 bytes .../Pot_Knobs/pot_knob_two_parts_cap.stl | Bin 10174 -> 0 bytes Latest commits for file Schematics/SynthMages.pretty/C_Rect_L22.0mm_W6.1mm_P20mm_MKT_BIG_RED_CAP.kicad_mod (grid_origin -1.27 106.172 (grid_origin 121.92 119.38 "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Paste" "Notes": "Layer F.Paste" "Notes": "Layer B.Paste" "Notes": "Layer F.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer B.Cu" "Notes": "Layer F.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Mask" "Notes": "Layer F.Paste" "Notes": "Layer F.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer B.Mask" "Notes": "Layer B.Cu" "Notes": "Layer B.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.SilkS" "Notes": "Layer B.Mask" "Notes": "Layer B.Paste" "Notes": "Layer F.Paste" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer B.Cu" "Notes": "Layer F.Mask" "Notes": "Layer F.Mask" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer F.Mask" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer B.Mask" "Notes": "Layer B.Cu" "Notes": "Layer F.SilkS" "Notes": "Layer B.Cu" "Notes": "Layer F.Paste" "Notes": "Layer F.SilkS" "Notes": "Layer B.Paste" "Notes": "Layer F.Paste" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer F.Cu" "Notes": "Layers L1/L2" "Notes": "Layer B.Cu" "Notes": "Layer B.SilkS" ; DRILL file {KiCad 7.0.11-7.0.11~ubuntu22.04.1} date Tue Mar 5 20:19:51 2024 Copper Layer Stackup: T5 15.200mm 0.5984" (1 hole) T3 7.000mm 0.2756" (6 holes T4 10.000mm 0.3937" (4 holes) (with 4 slots) T2 5.000mm 0.1969" (1 hole) Total plated holes count 16 Not plated through holes: ============================================================= 2dd0b8c0c736720a0b064bbe1304dc9562beb260 init 969311f00cbb6d6ece9a25b5fb1d4e2884e468c0 Module Spellbook Pages Fab Plant Research Table of Contents PSU (power supply unit Outputs.
- Hardware/PCB/precadsr/potsetc.kicad_sch Normal file Unescape // margins.
- 4.849723e-01 -7.073257e-03 8.745009e-01 vertex -1.084793e+02 9.695134e+01 9.130643e+00.