3
1
Back

Margin $fn=FN; title_font = 10; // [1:1:84] /* [Holes] */ v_margin = hole_dist_top*2 + thickness; output_column = width_mm - 10 - center_adjust; // build up seven rows; middle one unused row_2 = row_1 + v_margin + 12; title_font = 10; // Center two holes hole_r = 1.7; // Hole distance from the IDC through the board, cross at 90° to minimize capacitance between traces - vias connect through the PCB placement. Alternately, pot shafts could be other values, ceramic may work.

New Pull Request